An entity, which is able to interact with a controller by sending commands as per Non-Volatile Memory Express (NVMe) specifications, can be termed a Host. The NVMe or Non-Volatile Memory Host Controller Interface Specification (NVMHCI) is a logical device interface specification for accessing non-volatile storage media attached through a Peripheral Component Interconnect Express (PCIe) bus. A controller is associated with a single PCIe function that can process the commands and can send an appropriate response to the host as per the NVMe specification.
FIG. 1A is a schematic block diagram of a standard device and host interface 100 illustrating various components, according to related art. According to FIG. 1A, the host interface 100 comprises an NVMe storage device 102 acting as an SSD controller, a host 104, and an application 114 running on a user space. The host 104 and the NVMe device 102 interact with each other over a PCIe bus in a kernel space. The host 104 comprises an NVMe MiniPort driver 106, a windows storport driver 108, a windows class driver 110, and an input/output (IO) manager 112. Further, the host 104 runs one or more applications 114 in the user space.
FIG. 1B is a schematic diagram 120 illustrating interaction between a host 122 and controller 124, according to related art. According to FIG. 1B, the host 122 and the controller 124 interact with each other over a PCIe bus (not shown in the figure). A plurality of processes will be running on the host 122. The host 122 maintains queues for submitting the command and monitoring the status of each submitted command. The host 122 maintains an administrative submission queue and an administrative completion queue for submitting administrative commands, for execution, and reaping the outcomes that are completed by the controller 124, respectively. Further, the host 122 maintains I/O submission queue 1 and I/O completion queue 1, I/O submission queue 2 and I/O completion queue 2, I/O submission queue N and I/O completion queue N for monitoring a plurality of I/O commands/ requests received from the plurality of applications running on the host 122.
Solid-state drives (SSDs), including NAND flash memory, are commonly used as a storage entity in systems ranging from consumer products to enterprise-level computer systems. The NVMe host controllers in some SSDs often manage high-throughput data traffic between one or more hosts. A host controller interface standard, such as non-volatile memory expresses (NVMe), allows a large number of tasks to be performed in an out-of-order fashion. This may present a challenging problem for multi-core host controller SSDs.
According to NVMe specifications, an NVMe-based host controller should support the detection of a command ID conflict. A command ID conflict situation arises in an NVMe compliant SSD when more than one command with same command ID comes to the processing scope before the processing of a previously-submitted command gets completed. In such scenarios, the NVMe specification mandates processing the previous command with due merits and processing the rest of the commands, which have the same command with the same command identifier, with a conflict error.
Since in a completion entry only a submission queue (SQ) identifier (ID) and a command ID are present, it is impossible for a host to distinguish for which command a successful response has come and for which command a command ID conflict error response has been reported by the controller. As a consequence of this, it will be difficult for the host to release the corresponding resources associated with the command based on the response. For the proper release of the resources, the host has to wait until it receives completions for all the commands.